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1/22 may 2002 M48Z512A M48Z512Ay, M48Z512Av* 4 mbit (512 kbit x 8) zeropower ? sram * contact local sales office features summary n integrated, ultra low power sram, power-fail control circuit, and battery n conventional sram operation; unlimited write cycles n 10 years of data retention in the absence of power n automatic power-fail chip deselect and write protection n two write protect voltages: (v pfd = power-fail deselect voltage) C M48Z512A: v cc = 4.75 to 5.5v 4.5v v pfd 4.75v C M48Z512Ay: v cc = 4.5 to 5.5v 4.2v v pfd 4.5v C M48Z512Av: v cc = 3.0 to 3.6v 2.8v v pfd 3.0v n battery internally isolated until power is applied n pin and function compatible with jedec standard 512k x 8 srams n surface-mount chip set packaging (figure 2) includes a 28-pin soic and a 32- lead tsop (snaphat ? top to be ordered separately) n soic package provides direct connection for a snaphat top which contains the battery n snaphat housing (battery) is replaceable figure 1. 32-pin pmdip module figure 2. surface-mount (smt) solution pmdip32 (pm) module 32 1 tsop ii 32 (nc) (10 x 20mm) snaphat (sh) crystal / battery soh28 (mh) 32 1
M48Z512A, M48Z512Ay, M48Z512Av* 2/22 table of contents description ....................................................................3 logicdiagram(figure3.).........................................................3 signalnames(table1.)..........................................................3 dip connections (figure 4.) .......................................................4 blockdiagram(figure5.).........................................................4 hardware hookup for surface-mount (smt) solution (figure 6.) . . . ........................5 surface-mount (smt) solution (table 2.) . . ...........................................5 maximumrating.................................................................6 absolutemaximumratings(table3.) ...............................................6 dc and ac parameters. . ........................................................7 operating and ac measurement conditions (table 4.) ..................................7 acmeasurementloadcircuit(figure7.).............................................7 capacitance (table 5.) . . . ........................................................7 dccharacteristics(table6.) ......................................................8 operatingmodes...............................................................8 operating modes (table 7.) ........................................................8 readmode....................................................................9 chip enable or output enable controlled, read mode ac waveforms (figure 8.). . ...........9 addresscontrolled,readmodeacwaveforms(figure9.)..............................9 readmodeaccharacteristics(table8.)...........................................10 writemode..................................................................11 write enable controlled, write ac waveforms (figure 10.) ...........................11 chipenablecontrolled,writeacwaveforms(figure11.).............................11 writemodeaccharacteristics(table9.) ..........................................12 dataretentionmode............................................................13 powerdown/upmodeacwaveforms(figure12.) ....................................13 powerdown/upaccharacteristics(table10.).......................................13 powerdown/uptrippointsdccharacteristics(table11.)..............................14 v cc noise and negative going transients . ..........................................14 supplyvoltageprotection(figure13.)..............................................14 partnumbering ...............................................................15 snaphatbatterytable(table13.)................................................15 package mechanical information . . . ..........................................16 revisionhistory...............................................................21
3/22 M48Z512A, M48Z512Ay, M48Z512Av* description the M48Z512A/y/v zeropower ? ram is a non-volatile, 4,194,304-bit static ram organized as 524,288 words by 8 bits. the device combines an internal lithium battery, a cmos sram and a control circuit in a plastic, 32-pin dip module. for surface-mount environments st provides a chip set solution consisting of a 28-pin, 330mil soic nvram supervisor (m40z300/w) and a 32-pin tsop type ii (10 x 20mm) lpsram (m68z512/w) packages. both 5v and 3v versions are available (see table 2, page 5). the unique design allows the snaphat ? battery package to be mounted on top of the soic pack- age after the completion of the surface-mount pro- cess. insertion of the snaphat housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. the snaphat housing is keyed to pre- vent reverse insertion. the snaphat battery package is shipped sepa- rately in plastic anti-static tubes or in tape & reel form. the part number is m4z32-br00sh1. figure 3. logic diagram table 1. signal names ai02043 19 a0-a18 w dq0-dq7 v cc M48Z512A M48Z512Ay M48Z512Av g v ss 8 e a0-a18 address inputs dq0-dq7 data inputs / outputs e chip enable input g output enable input w write enable input v cc supply voltage v ss ground
M48Z512A, M48Z512Ay, M48Z512Av* 4/22 figure 4. dip connections figure 5. block diagram a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a15 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a16 a18 v cc ai02044 M48Z512A M48Z512Ay M48Z512Av 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 a12 a14 w a17 3 4 28 27 32 31 ai02045 internal battery e v cc v ss voltage sense and switching circuitry 512k x 8 sram array a0-a18 dq0-dq7 w g power e
5/22 M48Z512A, M48Z512Ay, M48Z512Av* figure 6. hardware hookup for surface-mount (smt) solution note: for pin connections, see individual data sheets for m48z300/300w and m68z512/512w at www.st.com. 1. connect ths pin to v out if 4.2v v pfd 4.5v (M48Z512Ay) or connect ths pin to v ss if 4.5v v pfd 4.75v (M48Z512A). 2. connect ths pin to v ss if 2.8v v pfd 3.0v (M48Z512Av). 3. snaphat ? top ordered separately. table 2. surface-mount (smt) solution note: 1. connection of threshold select pin (pin 13) of supervisor (m40z300/300w). nvram lpsram supervisor ths pin (1) M48Z512A m68z512 m40z300 v ss M48Z512Ay m68z512 m40z300 v out M48Z512Av m68z512w m40z300w v ss ai03631 e1 con v ss v out ths (2,3) a m40z300/w e b e2 con e3 con e4 con v ss e2 v cc m68z512/w e a0-a18 w dq0-dq7 snaphat battery (4) rst bl
M48Z512A, M48Z512Ay, M48Z512Av* 6/22 maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 3. absolute maximum ratings note: 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package: reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 to 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) C40 to 85 c t bias temperature under bias C40 to 70 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to 7 v v cc supply voltage M48Z512A/512ay C0.3 to 7.0 v M48Z512Av C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
7/22 M48Z512A, M48Z512Ay, M48Z512Av* dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 7. ac measurement load circuit note: excluding open drain output pins; 50pf for M48Z512Av. table 5. capacitance note: 1. effective capacitance measured with power supply at 5v (M48Z512A/y) or 3.3v (M48Z512Av); sampled only, not 100% tested. 2. outputs deselected. 3. at 25c. parameter M48Z512A/512ay M48Z512Av unit supply voltage (v cc ) 4.75 to 5.5v or 4.5 to 5.5 3.0 to 3.6 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 50 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v ai03903 c l = 100pf or 30 pf c l includes jig capacitance 650 w device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
M48Z512A, M48Z512Ay, M48Z512Av* 8/22 table 6. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc =4.75to5.5v,4.5to5.5v,or3.0to3.6v(exceptwherenoted). 2. outputs deselected. operating modes the M48Z512A/y/v also has its own power-fail detect circuit. the control circuitry constantly mon- itors the single v cc supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc .asv cc falls below the switchover voltage (v so ), the control cir- cuitry connects the battery which maintains data until valid power returns. the zeropower ? ram replaces industry stan- dard srams. it provides the nonvolatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. table 7. operating modes note: x = v ih or v il ;v so = battery back-up switchover voltage. 1. see table 11, page 14 for details. sym parameter test condition (1) M48Z512A/y M48Z512Av unit C70 C85 min max min max i li (2) input leakage current 0v v in v cc 1 1 a i lo (2) output leakage current 0v v out v cc 1 1 a i cc supply current e =v il outputs open 11 5 50 ma i cc1 supply current (standby) ttl e =v ih 10 4 ma i cc2 supply current (standby) cmos e 3 v cc C0.2v 53ma v il input low voltage C0.3 0.8 C0.3 0.6 v v ih input high voltage 2.2 v cc +0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 0.4 v v oh output high voltage i oh =C1ma 2.4 2.2 v mode v cc e g w dq0-dq7 power deselect 4.75 to 5.5v or 4.5 to 5.5v or 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
9/22 M48Z512A, M48Z512Ay, M48Z512Av* read mode the M48Z512A/y/v is in the read mode whenev- er w (write enable) is high and e (chip enable) is low. the device architecture allows ripple- through access of data from eight of 4,194,304 lo- cations in the static storage array. thus, the unique address specified by the 19 address inputs defines which one of the 524,288 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, provid- ingthatthee (chip enable) and g (output en- able) access times are also satisfied. if the e and g access times are not met, valid data will be available after the later of chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv .ifthead- dress inputs are changed while e and g remain low, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 8. chip enable or output enable controlled, read mode ac waveforms note: write enable (w )=high. figure 9. address controlled, read mode ac waveforms note: chip enable (e ) and output enable (g ) = low, write enable (w ) = high. ai01221 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz data out a0-a18 e g dq0-dq7 valid ai01220 taxqx data valid a0-a18 dq0-dq7 tavav tavqv
M48Z512A, M48Z512Ay, M48Z512Av* 10/22 table 8. read mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc =4.75to5.5v,4.5to5.5v,or3.0to3.6v(exceptwherenoted). 2. c l = 5pf. symbol parameter (1) M48Z512A/y M48Z512A/y/v unit C70 C85 min max min max t avav read cycle time 70 85 ns t av qv address valid to output valid 70 85 ns t elqv chip enable low to output valid 70 85 ns t glqv output enable low to output valid 35 45 ns t elqx (2) chip enable low to output transition 5 5 ns t glqx (2) output enable low to output transition 5 5 ns t ehqz (2) chip enable high to output hi-z 30 35 ns t ghqz (2) output enable high to output hi-z 20 25 ns t axqx address transition to output transition 5 5 ns
11/22 M48Z512A, M48Z512Ay, M48Z512Av* write mode the M48Z512A/y/v is in the write mode when- ever w and e are active. the start of a write is referenced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid throughout the cycle. e or w must return high for a minimum of t e- hax from e or t whax from w prior to the initiation of another read or write cycle. data-in must be valid t dveh or t dvwh prior to the end of write and remain valid for t ehdx or t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g ,alowonw will disable the outputs t wlqz after w falls. figure 10. write enable controlled, write ac waveforms note: output enable (g )=high. figure 11. chip enable controlled, write ac waveforms note: output enable (g )=high. ai01222 tavav twhax tdvwh data input a0-a18 e w dq0-dq7 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx ai01223 tavav tehax tdveh a0-a18 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
M48Z512A, M48Z512Ay, M48Z512Av* 12/22 table 9. write mode ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc = 4.75 to 5.5v, 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. c l = 5pf. 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) M48Z512A/y M48Z512A/y/v unit C70 C85 min max min max t avav write cycle time 70 85 ns t avwl address valid to write enable low 0 0 ns t avel address valid to chip enable low 0 0 ns t wlwh write enable pulse width 55 65 ns t eleh chip enable low to chip enable high 55 75 ns t whax write enable high to address transition 5 5 ns t ehax chip enable high to address transition 15 15 ns t dvwh input valid to write enable high 30 35 ns t dveh input valid to chip enable high 30 35 ns t whdx write enable high to input transition 0 0 ns t ehdx chip enable high to input transition 10 10 ns t wlqz (2,3) write enable low to output hi-z 25 30 ns t av wh address valid to write enable high 65 75 ns t av eh address valid to chip enable high 65 75 ns t whqx (2,3) write enable high to output transition 5 5 ns
13/22 M48Z512A, M48Z512Ay, M48Z512Av* data retention mode with valid v cc applied, the M48Z512A/y/v oper- ates as a conventional bytewide? static ram. should the supply voltage decay, the ram will au- tomatically power-fail deselect, write protecting it- self t wp after v cc falls below v pfd . all outputs become high impedance, and all inputs are treated as don't care. if power fail detection occurs during a valid ac- cess, the memory cycle continues to completion. if the memory cycle fails to terminate within the time t wp , write protection takes place. when v cc drops below v so , the control circuit switches power to the internal energy source which preserves data. the internal coin cell will maintain data in the M48Z512A/y/v after the initial application of v cc for an accumulated period of at least 10 years when v cc is less than v so . as system power re- turns and v cc rises above v so , the battery is dis- connected, and the power supply is switched to external v cc . write protection continues for t er af- ter v cc reaches v pfd to allow for processor stabi- lization. after t er , normal ram operation can resume. for more information on battery storage life refer to the application note an1012. figure 12. power down/up mode ac waveforms table 10. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a =0to70c;v cc =4.75to5.5v,4.5to5.5v,or3.0to3.6v(exceptwherenoted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. symbol parameter (1) min max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time M48Z512A/y 10 s M48Z512Av 150 t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t wpt write protect time M48Z512A/y 40 150 s M48Z512Av 40 250 t er e recovery time 40 120 ms ai02385 v cc inputs outputs don't care high-z twp tfb tr trb valid valid recognized recognized v pfd (max) v pfd (min) v so ter tf tdr (including e) v ss
M48Z512A, M48Z512Ay, M48Z512Av* 14/22 table 11. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a =0to70c;v cc =4.75to5.5v,4.5to5.5v,or3.0to3.6v(exceptwherenoted). 3. at 25c. v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sultinginspikesonthev cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (see figure 13) is recommended in order to provide the needed fil- tering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky diode from v cc to v ss (cathode con- nected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface-mount). figure 13. supply voltage protection symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage M48Z512A 4.5 4.6 4.75 v M48Z512Ay 4.2 4.3 4.5 v M48Z512Av 2.8 2.9 3.0 v v so battery back-up switchover voltage M48Z512A/y 3.0 v M48Z512Av 2.5 v t dr (3) expected data retention time 10 years ai02169 v cc 0.1 m f device v cc v ss
15/22 M48Z512A, M48Z512Ay, M48Z512Av* part numbering table 12. ordering information scheme note: 1. contact local sales office 2. the soic package (soh28) requires the battery package (snaphat ? ) which is ordered separately under the part number m4zxx-br00sh in plastic tube or m4zxx-br00shtr in tape & reel form. 3. contact sales offices for availability of extended temperature. caution : do not place the snaphat battery package m4zxx-br00sh in conductive foam as it will drain the lithium button-cell bat- tery. for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 13. snaphat battery table example: m48z 512ay C70 pm 1 device type m48z supply voltage and write protect voltage 512a = v cc = 4.75 to 5.5v; v pfd = 4.5 to 4.75v 512ay = v cc = 4.5 to 5.5v; v pfd = 4.2 to 4.5v 512av (1) =v cc = 3.0 to 3.6v; v pfd = 2.8 to 3.0v speed C70 = 70ns (for M48Z512A/y) C85 = 85ns (for M48Z512A/y/v) package (2) pm = pmdip32 temperature range 1 = 0 to 70c 9 = extended temperature (3) part number description package m4z28-br00sh lithium battery (48mah) snaphat sh m4z32-br00sh lithium battery (120mah) snaphat sh
M48Z512A, M48Z512Ay, M48Z512Av* 16/22 package mechanical information figure 14. pmdip32 C 32-pin plastic dip module, package outline note: drawing is not to scale. table 14. pmdip32 C 32-pin plastic dip module, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 C 0.015 C b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n32 32 pmdip a1 a l be1 d e n 1 ea e3 s c
17/22 M48Z512A, M48Z512Ay, M48Z512Av* figure 15. soh28 C 28-lead plastic small outline, battery snaphat, package outline note: drawing is not to scale. table 15. soh28 C 28-lead plastic small outline, battery snaphat, package mechanical data symbol mm inch typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 1.27 C C 0.050 C C eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a 0 8 0 8 n28 28 cp 0.10 0.004 soh-a e n d c l a1 a 1 h a cp be a2 eb
M48Z512A, M48Z512Ay, M48Z512Av* 18/22 figure 16. sh C 4-pin snaphat housing for 48mah battery, package outline note: drawing is not to scale. table 16. sh C 4-pin snaphat housing for 48mah battery, package mechanical data symb mm inches typ min max typ min max a 9.78 0.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
19/22 M48Z512A, M48Z512Ay, M48Z512Av* figure 17. sh C 4-pin snaphat housing for 120mah battery, package outline note: drawing is not to scale. table 17. sh - 4-pin snaphat housing for 120mah battery, package mechanical data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 0.335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 0.710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shzp-a a1 a d e ea eb a2 b l a3
M48Z512A, M48Z512Ay, M48Z512Av* 20/22 figure 18. tsop ii 32 C 32-lead plastic thin small outline ii, 10 x 20 mm, package outline note: drawing is not to scale. table 18. tsop ii 32 C 32-lead plastic thin small outline ii, 10 x 20 mm, package mechanical data symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.30 0.52 0.012 0.020 c 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 e 1.27 C C 0.050 C C e 11.56 11.96 0.455 0.471 e1 10.03 10.29 0.395 0.405 l 0.40 0.60 0.016 0.024 a 0 5 0 5 cp 0.10 0.004 tsop-d 16 17 cp a 1 l a1 a 32 d e b e1 e c a2
21/22 M48Z512A, M48Z512Ay, M48Z512Av* revision history table 19. revision history date revision details march 2000 first issue 07/19/00 m48z12av added 01/15/01 changed lpsram device (table 2) 12/19/01 reformatted; added temperature information (table 5, 6, 8, 9, 10, 11); remove chipset option from ordering information (table 12); remove reference to clock 02/08/02 remove 85ns speed grade (table 6, 8, and 9) 05/29/02 modify reflow time and temperature footnotes (table 3)
M48Z512A, M48Z512Ay, M48Z512Av* 22/22 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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